Better Video With Less Power - QuickLogic Introduces VEE Facing challenges with mobile display image quality and battery life? Join Amelia Dalton for a look at QuickLogic’s new devices with the Visual Enhancement Engine (VEE). Amelia chats with Brian Faith of Quicklogic about new technology that can dramatically improve image quality on mobile displays while extending battery life. (QuickLogic)
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Designing with the Embedded PowerPC 440 in Xilinx's Virtex-5 Amelia Dalton talks with experts from Xilinx and Micron about taking advantage of the power and features of the embedded PPC440 and Micron's DRAM. (Xilinx)
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Power Matters Trying to tame power consumption in your battery-powered device? Join Journal Webcasts host Amelia Dalton as she chats with Wendy Lockhart of Actel about how you can use ultra-low power programmable devices from Actel in even the most power-sensitive designs. (Actel)
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Creating Secure Mobile Devices With Open Kernel Labs OKL4 In this Chalk Talk, Amelia Dalton delves into the world of software security and microkernels in mobile devices with Gernot Heiser and Rob McCammon of Open Kernel Labs. (Open Kernel Labs)
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Low Power Design With Xilinx and Linear Technology. Join Amelia Dalton as she chats with Mark Moran of Xilinx and Afshin Odabaee of Linear Technology about low power FPGA based designs. (Xilinx)
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Designing Embedded Systems With Linux and low cost FPGAs Join Amelia Dalton as she chats with industry experts about simplifying embedded systems design with Linux running on low-cost programmable system-on-chip platforms.(Xilinx)
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Lowest Total System Cost With Xilinx Spartan-3
Amelia Dalton chats with Mark Moran of Xilinx about reducing your overall system cost with the Xilinx Spartan-3 family of FPGAs. (Xilinx and Nu Horizons Electronics)
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Low Cost FPGA with SerDes Lattice ECP2M
Amelia Dalton talks with Bertrand Leigh of Lattice Semiconductor about low-cost FPGAs with multi-gigabit SerDes interface capability. (Lattice Semiconductor)
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CES 2008
Did you miss CES? Amelia Dalton didn't! Watch Journal Webcasts coverage of the event now!
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Crossing the Gap between Algorithm and Hardware Implementation
Join Amelia Dalton as she learns how C++ and Catapult C Synthesis can accelerate the design, implementation, and verification of complex system-level algorithms.
(Mentor Graphics)
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Meeting The Challenges of FPGA Design With Synplify Premier.
Join Amelia Dalton as she investigates several new design technologies that address the top challenges faced by FPGA designers today. (Synplicity)
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Accelerate SoC and ASIC Verification Using FPGA Prototypes.
Join Amelia Dalton as she explores the methods of ASIC verification available today and why FPGA-based prototypes offer the most affordable and most powerful solution. (Synplicity)
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Advancing SoC Verification Methods
Today’s SoC designs are incredibly complex; recent process technology improvements and a quest for more feature packed devices reinforce the fact that this trend will continue without any pause. Refinement of current verification processes and deployment of advanced verification technology will prove more critical to ensure continued SoC project successes.
(Mentor Graphics)
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Real World Solutions for FPGAs
in Ultra Low Power Applications
Join Amelia Dalton as she examines the Low Power Reference Platform from Arrow, Altera, and Linear Technology - proving that FPGAs really can run on batteries. (Altera, Arrow, Linear)
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Did you miss the ARM Developers' Conference?
Join Amelia Dalton for Journal Webcasts' coverage of the event -- it'll be just like you were there! (Journal Webcasts)
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Approaching Yield in the Nanometer Age
This tutorial goes into detail on DFM technical challenges and solutions within both the business and historical context of the IC design and manufacturing process. It shows the importance of the fabless model as part of a more holistic DFM methodology, and includes demonstrations of what the new tools look like.(Mentor Graphics)
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Virtex-5 FPGAs and PlanAhead Deliver Maximum Performance.
Learn how Virtex®-5 FPGAs deliver the industry's highest performance in the shortest design time with the added bonus of consuming less power than competing solutions. With no trade offs between performance and low power, system designers can get better results in less time with Virtex-5 FPGAs when designing with ISE® design tools and PlanAhead™ analysis tool. (Xilinx)
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Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA.
Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA.
Discover how the complete Xilinx solution for PCI Express® including the Virtex®-5 FPGA Development Kit will quickly and efficiently get you started on a Virtex-5 design using PCI Express. (Xilinx)
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Discover How the Complete Virtex-5 PCI Express Solution Reduces Risks for Your Application
Discover How to Design With and Take Advantage of the PCI Express Hard Block in the Virtex-5 FPGA.
Discover how the complete Xilinx solution for PCI Express® including the Virtex®-5 FPGA Development Kit will quickly and efficiently get you started on a Virtex-5 design using PCI Express. (Xilinx)
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An Introduction to the Xilinx Virtex-5 FPGA Family
With up to 330,000 logic cells, 1,200 I/O pins, low-power RocketIO™ serial transceivers, built-in PCI Express® endpoint and Ethernet MAC blocks, along with other hardened IP, Virtex®-5 FPGAs offer integrated system-level capabilities that shrink design cycles and reduce system cost. (Xilinx)
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Enable High-Volume Applications
with New Low-Cost FPGAs
See how to lower your system costs while getting to market in a hurry with new high-functionality, low-power FPGAs. Wireless, video and image processing, and display designers can all benefit from this new FPGA family's application-optimized features that meet your system and business needs. (Altera)
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Implement PCIe, GbE & SRIO
with Altera's Low-Cost FPGAs
This 15-minute QuickCast offers an overview of Arria GX devices, Altera’s newest FPGA family with transceivers. Arria GX FPGAs support three protocols: PCI Express, Gigabit Ethernet, and Serial RapidIO™, giving you a low-cost coprocessing option for your next design.
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Addressing Size, Weight, and Power Constraints
From satellite to soldier, reducing system size, weight, and power (SWaP) are critical. Whether in manned or unmanned equipment, addressing SWaP constraints is required for building deployable platforms, adding functionality, and increasing performance. View this net seminar to learn new techniques for designing SWaP-sensitive applications. (Altera)
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